VHDL Code Generator for a Complex Multiplier
نویسندگان
چکیده
In this paper we present a VHDL code generator for a complex multiplier. The complex multiplier is based on a bit-parallel version of distributed arithmetic which reduces the hardware by nearly half compared to a straightforward implementation based on real multipliers. We choose an Overturned-Stairs adder tree to perform the summations in distributed arithmetic. The tree has a regular structure and the same speed as the optimal Wallace tree when the number of operands is less than 19. The VHDL code from generator have been verified with test bench and the generated code is fully synthesiable with standard synthesis tools. A full-custom cell library is currently being implemented in a 0.35 μ m CMOS process to further improve the performance.
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